Texas Instruments OMAP5912 Reference Manual page 709

Table 35. DMA Software Compatible Register (DMA_GSCR)
Bit Name
15:4 RESERVED
3 OMAP3_1_MAPPING
DISABLE
2:0 RESERVED
Table 36. DMA Software Reset Control Register (DMA_GRST)
Bit Name
15:1 RESERVED
0 SW_RESET
Table 37. DMA Hardware Version ID Register (DMA_HW_ID)
Bit Name
15:0
Table 38. PCh-2 Version ID Register (DMA_PCh2_ID)
Bit Name
15:0 PCH2_ID
SPRU755B
Base Address = 0xFFFE DC00, Offset = 0x04
Function
Reserved
OMAP3.1 mapping disable
0 = DMA compatible with OMAP 3.0/3.1 system
DMA interrupt line mapping and logical channel
configuration register address mapping (system
DMA I/O space).
1 = DMA compatible with OMAP_3.2 DMA. Maps
interrupt lines and logical channel configuration
register address mapping as defined for OMAP
3.2.
Compatibility is also dependent on the
OMAP3_1_Compatible_Disable bit in register
DMA_LCH_CCR.
Reserved
Base Address = 0xFFFE DC00, Offset = 0x08
Function
Reserved
DMA software reset control:
0: SW will always read this bit as 0.
1: Resets the whole DMA when software writes 1
to this bit (automatically clears to 0).
Base Address = 0xFFFE DC00, Offset = 0x42
Function
DMA version ID number
Base Address = 0xFFFE DC00, Offset = 0x44
Function
DMA PCh-2 version ID number
Direct Memory Access (DMA) Support
System DMA
R/W Reset
R/W ND
R/W 0
R/W ND
R/W Reset
R/W ND
R/W 0
R/W Reset
R 0x0001
R/W Reset
R 0x0001
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