Texas Instruments OMAP5912 Reference Manual page 150

Traffic Controller
Table 7. OCP-T1/OCP-T2 Registers
Name
OCPT1_PRIOR
OCPT1_PTOR1
OCPT1_PTOR2
OCPT1_PTOR3
OCPT1_ATOR
OCPT1_AADDR
OCPT1_ATYPER
OCPT_CONFIG_REG
OCPT2_PRIOR
OCPT2_PTOR1
OCPT2_PTOR2
OCPT2_PTOR3
OCPT2_ATOR
OCPT2_AADDR
OCPT2_ATYPER
Table 8. OCP Priority Registers 1 and 2(OCPT1_PRIOR and OCPT2_PRIOR)
Bit Name
31:16 RESERVED
15:12 OCP_PRIORITY
11:8 DMA_PRIORITY
7
92 OMAP3.2 Subsystem
Table 7 lists the 32-bit OCP-T1 and OCP-T2 registers. Table 7 through
Table 15 describe the register bits.
Base Address = FFFE CC00
Description
OCP-T1 LRU priority register
OCP-T1 dynamic priority time-out 1
OCP-T1 dynamic priority time-out 2
OCP-T1 dynamic priority time-out 3
OCP-T1 abort time-out
OCP-T1 abort address
OCP-T1 abort type
OCP target configuration register
OCP-T2 LRU priority register
OCP-T2 dynamic priority time-out 1
OCP-T2 dynamic priority time-out 2
OCP-T2 dynamic priority time-out 3
OCP-T2 abort time-out
OCP-T2 abort address
OCP-T2 abort type
Base Address = 0xFFFE CC00, Offsets = 0x00 and 0xD0
Function
Reserved. To ensure software compatibility, reserved
bit should be written to 0 and read value should be
considered undefined.
Number of consecutive accesses allowed for OCP-I
Number of consecutive accesses allowed for DMA
Reserved
R/W Offset
R/W 0x00
R/W 0xA0
R/W 0xA4
R/W 0xA8
R/W 0xAC
R 0xB0
R 0xB4
R/W 0xB8
R/W 0xD0
R/W 0xD4
R/W 0xD8
R/W 0xDC
R/W 0xE0
R 0xE4
R 0xE8
R/W Reset
R/W 0x0000
R/W 0000
R/W 0000
SPRU749A