Texas Instruments OMAP5912 Reference Manual page 212

Clock Generation and Reset Management
Table 71. MPU Reserved Register (ARM_CKOUT2)
Bit Name
31:0 RESERVED
Table 72. MPU Idle Enable Control Register 3 (ARM_IDLECT3)
Bit Name
31:6 RESERVED
5 IDLTC2_ARM
4 EN_TC2_CK
3 IDLTC1_ARM
154 OMAP3.2 Subsystem
Base Address = 0xFFFE CE00, Offset = 0x20
Function
Reading these bits gives undefined values. Writing
to them has no effect.
Base Address = 0xFFFE CE00, Offset = 0x24
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Selects the idle entry mode for TC2 clock.
0: The TC2 clock remains active when the MPU
enters the idle mode (ARM_CK stopped).
1: The TC2 clock is stopped in conjunction with the
MPU clock when the idle mode is entered. Cutting off
is based on IDLE/ACK protocol between CLKRST
and peripherals outside OMAP.
Enables the TC2 clock. This is a generic clock
supplied to peripherals outside OMAP boundary and
is at the same frequency as the TC clock.
0: The TC2_CK clock is stopped. Ensure that all
peripherals connected to TC2_CK are inactive before
setting 0 on EN_TC2_CK.
1: The TC2_CK clock is active.
Selects the idle entry mode for TC1 clock.
0: The TC1 clock remains active when the MPU
enters the idle mode (ARM_CK stopped).
1: The TC1 clock is stopped in conjunction with the
MPU clock when the idle mode is entered. Cutting off
is based on IDLE/ACK protocol between CLKRST
and peripherals outside OMAP.
R/W Reset
R/W 0x0000
R/W Reset
R/W 0x000
R/W 0
R/W 1
R/W 0
SPRU749A