Texas Instruments OMAP5912 Reference Manual page 183

4.2 OMAP3.2 Clock Generation
SPRU749A
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Power control for external device reset/power on (flash memory)
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Wake-up functions initiated by interrupts (MPU and DSP) and DMA
requests (traffic controller and TIPB) in the idle mode
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Initiation of the wake-up sequence by external devices during the idle
mode
The clock domains in the OMAP 3.2 hardware engine platform are
synthesized by the digital phase-locked loops (DPLL). The DPLL input clock
source (CK_REF) is supplied from the ULPD.
The DPLL1 output frequencies are programmable and can be further divided
down to provide clocks to the MPU, the DSP, and the TC domains. The MPU
domain, the DSP domain, and the TC domain are clocked from DPLL1.
This implementation offers the clock rate selection flexibility to adjust the clock
frequency of each clock domain and allows the OMAP 3.2 hardware engine
to adjust each clock domain to its optimal frequency. In addition, each domain
is further subdivided into subdomains so that each subdomain can be
independently activated/deactivated while the remaining part of the clock
network is in an idle state.
The OMAP clock system is organized around three main clock domains: MPU,
DSP, and TC clock domains.
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The MPU clock domain contains: MPU, MPU external peripheral clocks,
MPU watchdog timer, MPU internal timers, and MPU interrupt handler.
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The DSP clock domain contains: DSP, DSP MMU, DSP external
peripheral clocks, DSP watchdog timer, DSP internal timers, and DSP
interrupt handler.
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The TC clock domain contains: TC, L3 OCP-I, MPUI port interface, system
DMA controller, MPU TIPB bridges, and LCD controller, and OCP-T1 and
OCP–T2.
Figure 42 shows the clock generator module.
Clock Generation and Reset Management
OMAP3.2 Subsystem 125