Texas Instruments OMAP5912 Reference Manual page 168

Traffic Controller
Table 35. EMIFF SDRAM MRS Register (legacy for OMAP3.1)
Bit Field
31:10 Reserved
9 WBST
8:7 Reserved
6:4 CASL
3 S/I
2:0 PGBL
Note: After the memory exits self−refresh mode, the first thing the software should do is write to the EMIFF_MRS (legacy or
new) register so that the SDRAM's mode register is set properly.
Table 36. EMIFF SDRAM Configuration Register 2 (EMIFF_SDRAM_
CONFIG_2_REG)
Bit Field
31:3 Reserved
2 sd_auto_clk
1 Rfrsh_reset
0 Rfrsh_stdby
110 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x24
Description
Must be all 0
Write burst must be 0 (burst write same as burst read).
Must be 00.
CAS idle time must be set to 3 for a mobile DDR device:
001: Reserved
011: CAS idle time = 3 (default)
Serial = 0 / Interleave = 1 (must be serial)
Page burst length. Must be set to full page burst (111) for
SDRAM and burst of 8 (011) for DDR SDRAM.
Base Address = 0xFFFE CC00, Offset = 0x3C
Description
Must be all 0.
Allow controller to suspend its internal clocks when
idle. The clocks are automatically reenabled when
there is an autorefresh or host request.
0: Disable (Reset)
1: Enable
This bit must be set in conjunction with the CLK bit in
the SDRAM configuration register in order to turn off
the clock to the external SDRAM device. Also, the
PWD bit in the configuration register must be set to 1
for autogating to be effective.
Place the SDRAM into self_refresh when in reset
(active high).
Place the SDRAM into self_refresh when in standby
mode (active high).
R/W Reset
R 0x000000
R/W 0
R 00
R/W 011
R/W 0
R/W 111
R/W Reset
R 0x0000000
R/W 0
R/W 1
R/W 1
SPRU749A