Texas Instruments OMAP5912 Reference Manual page 346

Table 41. DSP MMU Idle Control Register (DSPMMU_IDLE_CTRL)
Bit Name
31:2 Unused
1 GL_PDE
0 AUTOGATING_EN
8 DSP Subsystem Clocking and Reset Control
9 System Operating Details
9.1 DSP Private Peripherals
SPRU750A
Base Address = FFFE D200, Offset = 054
Function
Global power-down enable
0 − DSPMMU clock is always running and autogating
works when it is enabled
1 − DSPMMU clock is totally shut off and autogatong
does not work
Enables/Disables autogating
The clock generator and system reset module (CLK and RST) manages
operations such as the reset sequences, the clock generation function, the
power-saving modes, idle controls, and setup for the OMAP5912. The clock
domains in the OMAP5912 platform are synthesized by the DPLL1. The DPLL
input clock source is externally supplied from the CLKIN pin.
The MPU manages the master clock configuration for the OMAP5912 device.
The DSP subsystem master clock DSP_CK is enabled at reset until the DSP
is enabled. The EN_DSPCK bit in the clock control register ARM_CKCTL
allows turning off the DSP_CK while the DSP is still in a reset state.
The CLKM2 module generates the individual clock domains for the DSP
subsystem. These clock signals have programmable frequencies based on
divisors of several possible input clock sources. CLKM2 is considered an MPU
private peripheral, except for configuration of subdomain clocks for the DSP
subsystem. See chapter 4 for more information on clocking.
The DSP private peripherals are connected to the DSP CPU by a private TIPB
bridge. This provides reduced latency for DSP access to these particular
peripherals. The private peripherals consist of the following modules:
-
Three general-purpose timers
-
A watchdog timer
-
An interrupt handler
DSP Subsystem Clocking and Reset Control
Reset
DSP Subsystem
R/W
0 R/W
0 R/W
83