Texas Instruments OMAP5912 Reference Manual page 1030

Table 19. DSP Control Timer Register (DSP_CNTL_TIMER) (Continued)
Base Address = 0xE100 5000, 0xE100 5800, 0xE100 6000, Offset = 0x00
1 AR
0 ST
Table 20. DSP Load Timer Value, 1/2 LSW (DSP_LOAD_TIMER_LO)
Base Address = 0xE100 5000, 0xE100 5800, 0xE100 6000, Offset = 0x04
Bit Name
15:0 DSP_LOAD_TIMER_
HI
Table 21. DSP Load Timer Value, 1/2 MSW (DSP_LOAD_TIMER_HI)
Base Address = 0xE100 5000, 0xE100 5800, 0xE100 6000, Offset = 0x06
Bit Name
15:0 DSP_LOAD_TIMER_LO
Table 22. DSP Read Timer Value, 1/2 LSW (DSP_READ_TIMER_LO)
Base Address = 0xE100 5000, 0xE100 5800, 0xE100 6000, Offset = 0x08
Bit Name
15:0 DSP_READ_TIMER_LO Value of the timer bits (15:0): To read a correct
SPRU759B
0: One-shot mode
1: Autoreload mode
0: Stop timer value decrement
1: Start timer value decrement
If one-shot mode is selected (AR = 0), this bit is
automatically reset by internal logic when the timer
value is equal to 0.
Function
This value is loaded when the timer passes through
0 or when it starts.
Function
This value is loaded when the timer passes
through 0 or when it starts.
Function
value for DSP 32-bit OS timer, the upper 16 bits
(from DSP_READ_TIMER_HI) must read prior
to reading this register.
OMAP3.2 Operating System Timer
R/W
R/W
R/W
W Undefined
R/W
W Undefined
R/W
R Undefined
Timers
0
0
Reset
Reset
Reset
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