Texas Instruments OMAP5912 Reference Manual page 949

Table 39. Interrupt Encoded Source Register for FIQ (DSP_SIR_FIQ)
Bit Name
15:4 Reserved
3:0 FIQ_NUM
Table 40. Interrupt Control Register (DSP_CONTROL_REG)
Bit Name
15:2 Reserved
1 NEW_FIQ_AGR
0 NEW_IRQ_AGR
Table 41. Software Interrupt Set Register (DSP_SISR)
Bit Name
15:0 DSP_SISR
SPRU757B
Offset: 0x06
Function
Indicates the encoded interrupt number that has an
FIQ request. Reading this register clears the
corresponding bit in the DSP_ITR if the interrupt is set
as edge-sensitive.
Offset: 0x08
Function
Writing a 1 resets the FIQ output, clears the source
FIQ register, and enables a new FIQ generation, reset
by internal logic. The corresponding bit of DSP_ITR
must be cleared first.
Writing a 1 resets an IRQ output, clears the source
IRQ register, and enables a new IRQ generation, reset
by internal logic. The corresponding bit of DSP_ITR
must be cleared first.
Offset: 0x0A
Function
Writing a 0 followed by a 1 to any bit generates an
interrupt to the DSP if the corresponding DSP_ILR
register is set as edge-triggered; otherwise, no
interrupt is generated.
Registers
R/W Reset
R 0000
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0x0000
Interrupts 51