Texas Instruments OMAP5912 Reference Manual page 547

SPRU753A
b) Oscillator mode:
SETUP_ANALOG_CELL2, is loaded with the related setup value
from the ULPD register that corresponds to the maximum time
between ramp-up time of the external voltage supply and LDO
stabilization time.
When the counter underflow is generated, it enables the oscillator.
Then the setup counter, SETUP_ANALOG_CELL3, is loaded with the
related setup value from the ULPD register that corresponds to the
stabilization delay of the oscillator.
When the counter underflow is generated, it globally enables the sys-
tem input clock to peripherals.
The clocks for the peripherals are restarted if the corresponding clock
request is active. These two setup stages are intended to allow the
supply voltage and the input system clock to be stable before enabling
the input clock to peripherals.
4) FSM1 enters the awake mode.
5) OMAP3.2 input clock is enabled. In external mode, the clock is effectively
restarted whenever the system input clock arrives.
6) OMAP3.2 deasserts the CHIP_IDLE signal.
7) ULPD releases the CHIP_WAKEUP signal high.
In this case, the
Power Management
Ultralow-Power Device
setup counter,
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