Texas Instruments OMAP5912 Reference Manual page 1062

Table 55. Timer Control Register (TIMER_CTRL_REG)
Bit Name
31:4 RESERVED
3 ARL
2 IT_ENA
1 TRB
0 TSS
SPRU759B
Base Address = 0xFFFB 9000, Offset = 0x08
Function
Reserved
Autoreload/start:
1: Autorestart mode
0: One-shot mode: when counter reaches zero,
an interrupt is generated and timer is stopped
Interrupt enable:
0: Interrupt disabled
1: Interrupt enabled
Timer reload bit:
Setting bit to 1 reloads the counter at next 32
kHz-clock rising edge. Once the counter is
reloaded, the bit is reset.
Timer start/stop:
0: Stop timer
1: Start timer
If timer is in one-shot mode (ARL = 0), the bit is
automatically reset when the timer = 0.
Writes to this register must be separated by at least one 32-kHz clock period.
Operating System Timer
R/W Reset
R 0x0000 000
R/W 1
R/W 0
R/W 0
R/W 0
Timers 59