Texas Instruments OMAP5912 Reference Manual page 459

Configuration
Table 13. Functional Multiplexing Control 2 Register (FUNC_MUX_CTRL_2)
Bit Name
12:7 CONF_DSP_INT_SEL_R
6:0 CONF_ARM_INT_SEL_R
Table 14. Compatibility Mode Control 0 Register (COMP_MODE_CTRL_0)
Bit Name
31:16 CONF_COMP_
RESERVED_R
15:0 CONF_MUX_EN_R
42 Initialization
Base Address = 0xFFFE 1000, Offset Address = 0x08
Function
Select the DSP level 2 interrupts to be
observed.
The pin configuration for each observation
mode is specified (See Section 2.3).
Observing interrupts is done after multiplexers
that select between level and edge activity.
Select the MPU level 2 interrupts to be
observed.
The pin configuration for each observation
mode is specified (See Section 2.3).
Observing interrupts is done after multiplexers
that select between level and edge activity.
Base Address = 0xFFFE 1000, Offset Address = 0x0C
Function
Reserved for future expansion. These bits must
be written to 0x0000h
A value of 0xEAEF must be written to this
register to enable the pin multiplexing controlled
by the registers FUNC_MUX_CTRL (3-12),
PU_PD_SEL(0-4), and PULL_DWN_CTRL
(0-4). The boot code must configure all the pin
multiplexing registers FUNC_MUX_CTRL
(3-12), PU_PD_SEL(0-4), and
PULL_DWN_CTRL (0-4) first. Writing 0xEAEF
enables all the pin multiplexing to take effect
simultaneously.
This is the I/O multiplex enable register. At reset, any value written to the
registers FUNC_MUX_CTRL
PULL_DWN_CTRL (0-4) does not change the configuration of the pins.
However, setting the COMP_MODE_CTRL_0 register to 0x0000EAEF
activates:
Generic multiplexing registers: FUNC_MUX_CTRL_x, x ∈{3..12}
-
Pullup/pulldown enable registers: PULL_DWN_CTRL_y, y ∈{0..4}
-
Pullup/pulldown select registers: PU_PD_SEL_z, z ∈{0..4}
-
R/W
R/W
R/W
R/W
R/W
R/W
(3-12), PU_PD_SEL(0-4),
Reset
0x00
0x00
Reset
0x0000
0x0000
and
SPRU752B