Texas Instruments OMAP5912 Reference Manual page 171

Table 40. EMIFF DDR SDRAM Register (EMIFF_EMRS0)
Bit Field
31:10 Reserved
9:3 Unused
2 QFC
1 DS
0 DLL
Table 41. EMIFF Low Power SDRAM Register (EMIFF_EMRS1)
Bit Field
31:10 Reserved
9:5 Unused
SPRU749A
Note that there is only one physical MRS register. Using that address, no
automatic initialization sequence is generated; only a LOAD MODE register
command is issued.
A CPU write to this register generates a LOAD MODE register command, with
BA1,BA0 = 0,0.
Base Address = 0xFFFE CC00, Offset = 0x74
Description
Must be all 0.
No special function, but these bits are passed to the
memory.
QFC enable bit.
0: Disabled
1: Enabled
DS driver strength bit.
0: Normal
1: Reduced
DLL enable bit.
00: Enabled
1: Disabled
This register is used for DDR SDRAM memory only. It provides access to
extended configuration fields. The description is given here with reference to
standard devices, but must be checked with the specification of the device
actually used in a given application.
A CPU write to this register generates a LOAD MODE register command, with
BA1=0 and BA0 = 1. Twelve bits can be loaded.
Base Address = 0xFFFE CC00, Offset = 0x78
Description
Must be all 0.
No special function, but these bits are passed to the
memory.
Traffic Controller
R/W Reset
R 0x0000000
R/W
R/W
R/W
R/W
R/W Reset
R 0x000000
R/W
OMAP3.2 Subsystem
0x00
0
0
0
0000
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