Texas Instruments OMAP5912 Reference Manual page 210

Clock Generation and Reset Management
Table 69. MPU Clock Reset Status Register (ARM_SYSST) (Continued)
Bit Name
3 ARM_MCRST
2 ARM_WDRST
1 GLOB_SWRST
0 DSP_WDRST
152 OMAP3.2 Subsystem
Base Address = 0xFFFE CE00, Offset = 0x18
Function
Indicates whether or not an MPU reset has occurred.
This bit is cleared to 0 upon an external reset pulse
asserting at the CHIP_nRESET pin, or by writing to it a
logic 0. This bit cannot be written to logic 1 from the
TIPB interface.
0: The MPU processor has not been reset.
1: The MPU processor has been reset.
Indicates whether or not the reset has been asserted
due to an MPU timer/watchdog underflow. This bit is
cleared to 0 upon an external reset pulse asserting at
the CHIP_nRESET pin, or by writing to it a logic 0. This
bit cannot be written to logic 1 from the TIPB interface.
0: An MPU timer/watchdog underflow has not
occurred.
1: An MPU timer/watchdog underflow has generated
the reset.
Indicates whether or not the reset has been asserted
due to global software reset (DSP_EN set to 0 and
ARM_RST set to 1). This bit is cleared to 0 upon an
external reset pulse asserting at the CHIP_nRESET
pin, or by writing to it a logic 0. This bit cannot be
written to logic 1 from the TIPB interface.
0: Global software reset has not been requested.
1: Global software reset has been requested.
Indicates whether or not the reset has been asserted
due to DSP timer/watchdog underflow. This bit cannot
be written to logic 1 from the TIPB interface.
0: A DSP timer/watchdog underflow has not occurred.
1: A DSP timer/watchdog underflow has generated the
reset.
R/W Reset
R/C 1
R/C 0
R/C 0
R/C 0
SPRU749A