Texas Instruments OMAP5912 Reference Manual page 209

Table 69. MPU Clock Reset Status Register (ARM_SYSST)
Bit Name
31:14 RESERVED
13:11 CLOCK_SELECT
10:7 RESERVED
6 IDLE_DSP
5 POR
4 EXT_RST
SPRU749A
Base Address = 0xFFFE CE00, Offset = 0x18
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Reading these bits indicates the clock_select pins and
indicates the current clocking mode selection. Writing
to these bits enables switching the OMAP3.2 clocking
scheme.
These bits are at logic 0 after reset:
000: Fully synchronous
001: Reserved
010: Synchronous scalable
011: Reserved
100: Reserved
101: Bypass
110: Mix mode #3, MPU synchronous to TC, DSP
MMU synchronous scalar to MPU and TC
111: Mix mode #4, DSP MMU synchronous to TC,
MPU synchronous scalar to DSP MMU and TC
These read only bits are undefined.
Indicates the DSP state.
0: The DSP is active.
1: The DSP is in global-idle state.
Indicates (in conjunction with EXT_RST bit) whether or
not a power-on reset (cold start) has occurred. Writing
it to logic 0 clears this bit. This bit cannot be written to
logic 1 from the TIPB interface.
0: No power-on-reset has been detected.
1: A power-on-reset has occurred.
Indicates that external reset has been asserted. Writing
it to logic 0 clears this bit. This bit cannot be written to
logic 1 from the TIPB interface.
0: No external reset has been detected.
1: An external reset has occurred.
Clock Generation and Reset Management
R/W
R/W
R/W
R/C
R/C
OMAP3.2 Subsystem
Reset
00
000
R 0
R 0
1
1
151