Texas Instruments OMAP5912 Reference Manual page 245

Table 102. DSP SARAM Configuration Map (Continued)
API SIZE
0x0034−0x0035
0x0036−0x0037
0x0038−0x0039
0x003A−0x003B
0x003C−0x003D
0x003E−0x003F
0x0040−OTHERS
5.4 DSP Endianism Register
Table 103. DSP Endianism Register (DSP_ENDIAN_CONV)
Bit Name
31:2 Reserved
1 SWAP
0 EN
6 Mailboxes
6.1 Mailbox Registers
SPRU749A
SARAM SARAM SARAM
28 24
0000 0011 1111
0000 0111 1111
0000 1111 1111
0001 1111 1111
0011 1111 1111
0111 1111 1111
1111 1111 1111
This table decodes API_SIZE value into the exclusively accessible portion of
SARAM. The SARAM has 32 blocks (SARAM0 through SARAM31) on 2 KB
boundaries.
The exclusively accessible memory (host-only RAM) is marked with a 1, and
nonexclusively accessible memory (shared access RAM) is marked with a 0.
Note that this reigster is part of the Traffic Controller block.
Address = 0xFFFE CC34
Function
Reserved
0: Byte swap
1: Word swap
0: Disables DSP Endianism conversion
1: Enables DSP Endianism conversion
This register controls endianism for all DSP accesses through the traffic
controller.
-
The MPU/DMA/OCP-I uses the following registers to communicate with
the DSP:
SARAM SARAM
20 16 12
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
Mailboxes
SARAM SARAM
8 4
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
R/W
R
R/W
R/W
OMAP3.2 Subsystem
SARAM
0
1111
1111
1111
1111
1111
1111
1111
Reset
ND
0
0
187