Texas Instruments OMAP5912 Reference Manual page 934

Level 1 MPU Interrupt Handler
3.1.2 Software Interrupt
36 Interrupts
One interrupt level register (ILR) is associated with each incoming interrupt.
ILR determines whether the interrupt is to be edge-triggered or level-sensitive
and assigns it a priority level: 0 (the highest priority), 1, ... 30, 31 (the lowest
priority). If several interrupts have the same priority level assigned, they are
serviced in a predefined order: IRQ_31, IRQ_30, ..., IRQ_1, IRQ_0. ILR also
allows routing each of the 32 interrupts to either FIQ or IRQ.
The IRQ or FIQ outputs can be reset by writing a 1 to the corresponding bit of
the CONTROL_REG to enable new IRQ or FIQ generation. The writing also
clears the SIR_IRQ or SIR_FIQ register. The corresponding bit in the ITR must
be cleared before writing to the CONTROL_REG.
The interrupt handler also provides a 32-bit software interrupt register (SIR),
which corresponds to the same 32-bit external interrupt lines. Writing a 0
followed by a 1 to the targeted bit generates an interrupt if the corresponding
ILR is set to edge-sensitive; otherwise, no interrupt is generated.
An external interrupt request and an internal software request are merged
before being sent to the interrupt handler to be serviced. The software interrupt
register is always read as 0. You can use this software interrupt mechanism
to simulate an external interrupt and test the corresponding interrupt driver as
long as the interrupt line is programmed as edge-sensitive.
All internal interrupts are brought to the OMAP 3.2 subchip level to provide
maximum flexibility for system integration. You can reorganize, regroup, add,
or delete the interrupt inputs for your applications.
Figure 4 shows the MPU interrupt handler.
SPRU757B