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Table 30. Global Mask Interrupt Register (GMR)
Bit
Name
31:1
Reserved
0
GLOBAL_MASK
4
DSP Level 1 and Level 2.0 Interrupt Handler and Interface
4.1
Description
4.1.1
Interrupt Control and Configuration
SPRU757B
DSP Level 1 and Level 2.0 Interrupt Handler and Interface
The user can program the SIR register to emulate the interrupt generation. The
corresponding ILR must be programmed as edge-sensitive while using SIR
register. The procedure to generate an edge-sensitive interrupt is: SIR(bit i) =
0 − SIR(bit i) = 1 (rising edge generated). SIR will not be cleared automatically
(user must program it). A zero is always returned from a read to this register.
External interrupts are merged with the software interrupts before they are
sent to the MIR mask register for interrupt masking.
Offset: 0xA0
Function
When 1, the interrupt handler module and the output
signal INT_DIS are set to 1. (INT_DIS is the output
signal that indicates the interrupt handler has been
disabled.)
For power management, CLK&RST can turn off the
interrupt handler functional clock. A handshaking
protocol is defined for the CLK&RST module to idle or
wake up the interrupt handler.
DSP interrupts are handled through two cascaded interrupt controllers:
The DSP interrupt interface (level 1 handler) handles 24 interrupts.
-
The DSP interrupt handler (level 2.0 handler) handles 16 level 2 interrupts
-
that are routed to the DSP interrupt interface through low-priority interrupt
request (IRQ) and fast-priority interrupt request (FIQ).
If an interrupt occurs, the DSP_ITR register stores the incoming interrupt in the
corresponding bit. When there are several incoming interrupts, the DSP
interrupt handler compares the priority level of the interrupts before sending
an IRQ or FIQ to the DSP core. The selected interrupt number is stored in
DSP_SIR_IRQ or DSP_SIR_FIQ for the DSP to determine which interrupt
service routine to execute. Reading either of these registers by the DSP resets
the corresponding bit in DSP_ITR. The DSP can also individually clear each
bit in DSP_ITR by writing a 0 to the corresponding bits. Writing a 1 keeps its
previous value.
R/W
Reset
R/W
0
Interrupts
43
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