Texas Instruments OMAP5912 Reference Manual page 442

Table 6. Input/Output for Clock and Reset (Continued)
Pin Name Dir.
SYS_CLK_IN IN
EXT_CLK IN
EXT_48M IN
BCLKREQ IN
MCLKREQ IN
CLK32K_OUT OUT
EXT_MASTER OUT
_REQ
RST_HOST_ OUT
OUT
BCLK OUT
MCLK OUT
SPRU752B
Ball Descrip- Default Mode in
tion RESET_MODE 0
Y4 12-MHz to
19.2-MHz
clock in
N18 External
clock for
GP timers
N21 Backup
48-MHz
clock in
W15 Request for
BCLK
R10 Request for
MCLK
R13 32-kHz
clock out
R10 Request for
external
clock
W13 Modem
shut down if
battery fails
Y15 System
clock or
derived
from APLL
clock
V5 System
clock or
derived
from APLL
clock
Default Mode in
RESET_MODE 1
No Yes
No No
No No
Yes Yes
Yes Yes
Yes No
No No
No No
Yes Yes
Yes
Reset Architecture
Notes
Must be tied low if
on-chip oscillator is
used. Must select
mode 110 for Ball
Y4 with software.
Through GPIO14
input pin. Used if
on-chip APLL is
disabled.
Can be controlled
by software
(POWER_CTRL_
REG[3] if
POWER_CTRL_
REG[2]=0)
Can be divided
further by setting
SDW_CLK_DIV_C
TRL_SEL[7:2]
When 48MHz, can
be divided further
by setting
COM_RATIO_
SEL[7:2]
Initialization 25