Texas Instruments OMAP5912 Reference Manual page 142

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Traffic Controller

EMIFF DDR Data Writes (with respect to DLL)

1) T1: Fine tune delay control for shifting the data (a manual adjustment). 64 steps of adjustment with a step value

of 26.3ps (6 bit signed value in EMIFF_DLL_WRD_CTRL.WO). Note that 26.3 ps is a value valid in a nominal pro-

cess at room temp and is subject to variation across process and temperature.

2) T2: The DLLPhase control bit selects between whether or not the data is shifted 72 or 90 degrees (20% or 25%

delay) from the strobe.

Controlled Delay Subsystem Block Diagram

DLLPhase (rd)

LOADDLL (rd)

Read Offset (LDQS)

Read Offset (UDQS)

OMAP3.2 Subsystem

Figure 40 shows the controlled−delay block architecture. This block is

configured by the EMIFF DLL control register (bit fields from this register are

highlighted using bold characters).

DLLPhase (wr)

LOADDLL (wr)

Delayed-LDQS

Delayed-UDQS

Write Offset (clock)

Chapters

Table of Contents