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SPRU753A
c) The MPU programs the IDLDPLL_ARM and IDLIF _ARM bits of
ARM_IDLECT1 to allow TC and DPLL to go into idle mode.
d) The MPU programs the MPU interrupt handlers to mask/unmask
interrupts and ensure the wake-up path.
e) The MPU programs the SOFT_DISABLE_REQ_REQ register of
ULPD to ensure a wake-up path.
f)
The MPU clears POWER_CTRL_REG[4] of ULPD (ULPD big sleep
mode)
g) MPU executes the STANDBYWFI instruction.
h) All OMAP MPU and TC clock domains are automatically shutdown by
the CLKRST module.
i)
DPLL is automatically put in idle by the CLKRST module.
j)
CLKRST asserts the CHIP_IDLE signal to the ULPD.
k) The ULPD disables the OMAP3.2 input clock and asserts the
CHIP_WAKEUP signal.
l)
The ULPD FSM automatically moves into sleep mode. The MPU
domain is in inactive state.
7) MPU active to pending state transition
a) The MPU places the external SDRAM in self-refresh mode (program
EMIFF register).
b) The MPU programs the ARM_IDLECT1, ARM_IDLECT2, and
ARM_IDLECT3 registers to ensure that all OMAP MPU and TC
subdomain clocks are shut down.
c) The MPU programs the IDLDPLL_ARM and IDLIF_ARM bits of
ARM_IDLECT1 to allow TC and DPLL to go into idle mode.
d) The MPU programs the MPU interrupt handlers to mask/unmask
interrupts and ensure the wake-up path.
e) The MPU programs the SOFT_DISABLE_REQ_REQ register of the
ULPD to ensure the wake-up path.
f)
The MPU sets bit POWER_CTRL_REG[4] of the ULPD (ULPD deep
sleep mode).
g) The MPU sets bit POWER_CTRL_REG[0] of the ULPD (LOW_PWR
feature enabled).
h) The MPU sets/clears bit POWER_CTRL_REG[9] of the ULPD
(oscillator control).
OMAP5912 Power Modes
Power Management
101
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