Texas Instruments OMAP5912 Reference Manual page 730

System DMA
Table 71. DMA Channel Control Register 2 (DMA_CCR2)
Base Address = 0xFFFE D800, Offset Address = 0x24 + n*0x40
Bit Name
15:3 RESERVED
2 BS
1 TCE
0 CFE
Table 72. DMA Logical Channel Link Control Register (DMA_CLNK_CTRL)
Base Address = 0xFFFE D800, Offset Address = 0x28 + n*0x40
Bit Name
15 EL
14 SL
13:5 RESERVED
4 NID
3:0 NID
106 Direct Memory Access (DMA) Support
Function
Reserved
Block Synchronization
Transparent copy enable
Constant fill enable
BS: Block synchronization
-
This bit and the fs bit in the DMA_CCR register are used to program the
way that a DMA_request is serviced in a synchronized transfer.
Transparent copy enable
-
1: Transparent copy operation is enabled. During transparent copy opera-
tion, any source data type that matches the DMA_COLOR_U/L registers
is not written to the destination.
0: Transparent copy operation is disabled. During transparent copy opera-
tion, any source pixel is written to the destination (No mask, brush are sup-
ported).
Constant fill enable
-
1: Constant fill operation is enabled. During constant fill operation, it writes
destination with DMA_COLOR_U/L, instead of data from source.
0: Constant fill operation is disabled. During BLT operation, any source
data is written to the destination without constant fill.
Function
Enable_Lnk
Stop_Lnk
Reserved
Next LCh_ID
Next LCh_ID
R/W Reset
R/W N/A
R/W N/A
R/W N/A
R/W N/A
R/W Reset
R/W 0
R/W 0
R/W N/A
R/W 0
(read
as 0)
R/W 0000
SPRU755B