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Memory Interfaces for the EMIFS
Figure 8.
Multiplane Copy-Back Operation
T r
R/B_
00h
Address
2.1.7
Read Status and Read Multiplane Status Operations
Table 7.
Status Register Mapping for 32, 64, 128, and 256 Megabits
32
Memory Interfaces
address, R/B_ remains in a busy state for a short period of time. When the last
command operation 0x10 is sent, thel programming of the NFMC starts and
the NFMC drives its R/B_ signal low. A read status operation (command 0x70
or 0x71) can be issued to find out when the NFMC returns to ready state by
polling the Ready/Busy_ bit in the status register (bit 6). Once the multiplane
copy-back program is finished, any additional partial-page programming into
the copied pages is prohibited before an erase operation. If not masked, an
interrupt is asserted each time R/B_ returns to high state. Typically, T
and T
are 12µs, 1µs, and 200µs, respectively (see Figure 8).
prog
T r
03h
Address
8Ah
Up to 3 times
The NFMC has a status register, which can be accessed to determine whether
a program or erase operation was completed, and whether the ongoing
operation was completed successfully. After writing command 0x70 or 0x71
to the NND_COMMAND_SEC register, an access to the NAND controller
access register (NND_ACCESS) drives the content of the NFMC status
register on the multiplexed 8-bit bus.
The NFMC remains in read status mode until further commands are issued to
it. Therefore, if the status register is read during a random read cycle, a read
command (0x00) must be issued before a sequential-page read cycle.
For the read status of a multiplane program or multi-erase operations, the read
multiplane status command (71h) must be used rather than 70h. (See Table 7
and Table 8).
Bit
Definition
7
Write protect
6
Device operation
T dbsy
Address
11h
Up to 3 times
Read Status (70h)
0: Protected
1: Not protected
0: Busy
1: Ready
T prog
8Ah
Address
D0h
SPRU756A
, T
,
r
dbsy
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