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4.2.4
DSP Clock Domain
SPRU749A
Even when the MPU is not in idle mode, you have the option of individually
disabling the clock to the MPU subdomains via the ARM_IDLECT2 register.
This allows power saving when a module is not used.
Depending on the OMAP clocking mode, the DPLL1 output frequency defines
the speed of the DSP domain. The clock output from DPLL1 (CK_GEN2) can
be further divided in order to supply the clock of the DSP and its subsystems.
At reset, DPLL1 is in bypass mode (CK_GEN1 = CK_GEN2 = CK_REF).
The DSP clock domain is divided into six subdomains:
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DSP (DSP_CK)
The clock signal driving the DSP can be further divided by 2, 4, or 8 by pro-
gramming the divide-down bits DSPDIV of ARM_CKCTL register. At
reset, the highest frequency (divided by 1) is selected and DSP_CK =
CK_GEN2 = CK_REF.
-
DSP MMU (DSPMMU_CK)
The clock signal driving the DSP MMU (DSPMMU_CK) can be further di-
vided by 2, 4, or 8 by programming the divide-down bits DSPMMUDIV of
the ARM_CKCTL register. At reset, the highest frequency (divided by 1) is
selected but the DSP MMU clock is inactive.
Note:
You must program DSPDIV and DSPMMUDIV so that the DSPMMU_CK
clock frequency is either one or one half times the DSP_CK clock frequency.
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DSP external peripheral clock (DSPPER_CK)
The DSP external peripheral clock can be further divided by 2, 4, or 8 by
programming the divide-down bits PERDIV of the DSP_CKCTL register.
DSPXOR_CK, a gated version of the CK_REF, can also be used to supply
the external peripherals. This clock is inactive at reset.
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DSP watchdog timer (DSPWDT_CK)
DSP watchdog timer is supplied with a low-frequency clock (CK_REF/14).
This clock is active at reset.
-
DSP internal timers (DSPTIM_CK)
The TIMXO bit of the DSP_CKCTL register selects either CK_GEN2 divid-
ed by 2, or the input reference clock (CK_REF) to supply the internal DSP
Clock Generation and Reset Management
OMAP3.2 Subsystem
131
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