Texas Instruments OMAP5912 Reference Manual page 137

3.3.3 Memory Mode Registers
3.3.4 EMIFF SDRAM Configuration
SPRU749A
This procedure is also suitable for the mobile DDR device, as this kind of
device does not include delay-locked loop technology (DLL).
The following restrictions apply to the MRS register programming:
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Burst length must be programmed to full page for SDR devices.
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For mobile DDR devices, burst length must be programmed to 8 and the
CAS idle time must be set to 3.
All SDRAM internal mode registers are mirrored in the EMIFF controller.
Standard MRS is provided. EMRS0 is provided for the DDR EMRS register.
EMRS1 is provided for low-power SDRAM new features (such as partial array
self-refresh, or temperature compensated self-refresh). EMRS2 is provided
for future use.
For each register write access, a 12-bit data value is loaded in the memory
device to support future new option bits in the existing registers. Always write
0 in all reserved bits.
When reading to these registers, the data in the mirrored register is returned.
The EMIFF SDRAM configuration register must then be programmed to define
the other parameters of the interface:
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Power-down strategy. When the PWD bit is set to 1, the power-down state
is automatically entered between memory accesses (see Table 31). When
there is no active transaction on the interface, CKE goes low. Any new
access request awakes the device before making the access.
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SDRAM autorefresh control.
To optimize SDRAM bandwidth usage for data transfer, it is preferable to
generate a sequence of autorefresh requests rather than a single autorefresh
request. A sequence of four or eight successive autorefreshes can be
programmed.
The autorefresh burst request is generated when a 16-bit refresh timer (see
SDRAM configuration register, see Table 31) reaches the following user
defined values, according to selected SDRAM frequency (via SDRAM
configuration register):
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Memory size and configuration
Traffic Controller
OMAP3.2 Subsystem 79