Texas Instruments OMAP5912 Reference Manual page 255

Multimedia processor device overview and architecture
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Table 117. TIPB Registers
Base Address = 0xFFFE D300 (public), 0xFFFE CA00 (private)
Name
RHEA_CNTL
RHEA_BUS_ALLOC
ARM_RHEA_CNTL
ENH_RHEA_CNTL
DEBUG_ADDRESS
DEBUG_DATA_LSB
DEBUG_DATA_MSB
DEBUG_CTRL_SIGNALS
ACCESS_CNTL
Table 118. TIPB Control Register (RHEA_CNTL)
Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x00
Bit
Name
15:8
TIMEOUT
SPRU749A
Table 117 provides a list of the TIPB registers. Table 118 through Table 126
provide register bit descriptions.
Description
TIPB control
TIPB allocation control
MPU TIPB control
EnhancedTIPB control
Debug address
Debug data LSB
Debug data MSB
Debug control signals
Access control
Function
TIPB bus access time-out.
When starting an access on TIPB bus, the time-out counter
is loaded with this value. If the current access is not finished
when the counter reaches 0, the cycle is aborted and abort
indications are given to the peripheral and the MPU, DMA,
or OCP-I.
Maximum value for TIMEOUT is 255.
TIPB Bridge
R/W
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
R/W
R/W
OMAP3.2 Subsystem
Reset
0xFF
197

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