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Ultralow-Power Device
Figure 7.
OMAP3.2-Initiated Wake-up Sequence
2
CLK32K_IN
CK_REF
(Internal
system clock)
ULPD_STATE
CHIP_IDLE
(internal signal)
CHIP_WAKEUP
(internal signal)
LOW_PWR
OMAP3.2 wake−up
request (internal)
30
Power Management
Deep sleep
The wake-up sequence requires five CLK32K clock cycles from assertion of
OMAP3.2 wake-up request to release of CK_REF.
-
Sequence 2
1) The following wake-up events occur:
a) MPU_RST low event
b) 32-kHz watchdog time-out
2) ULPD performs the transition to awake as described previously and
releases the system clock to OMAP3.2.
3) As soon as the system clock is back on, the ULPD asserts low the
OMAP3.2 reset for at least 30 system clock cycles.
4) On detection of OMAP3.2 reset low, OMAP3.2 deasserts the CHIP_IDLE
signal.
5) ULPD asserts the CHIP_WAKEUP signal high.
Awake sequence
4 CK_REF
Awake state
SPRU753A
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