Texas Instruments OMAP5912 Reference Manual page 928

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
Table 8. Mask Interrupt Register (MIR)
DW-1 † DW-2
@0x04 MIR-
DW-1
Access RW RW
Default 1
†
DW = 32 for the MPU interrupt handler; DW = 16 for the DSP interrupt handler.
Table 9. Source IRQ Register (SIR_IRQ)
@0x10
Access
Default
†
CODE_NB_IT = 7 for the MPU interrupt handler; CODE_NB_IT = 6 for the DSP interrupt handler.
30 Interrupts
In case of an edge-sensitive interrupt, when the host accesses the SIR_IRQ
or SIR_FIQ register, the bit corresponding to the currently active interrupt is
reset. For level-sensitive interrupts, this bit is simply the interrupt line current
state (after resynchronization).
The host can also clear each bit individually. To do this, it must write a 0 to the
corresponding bit. Write access to this register is stalled as long as the actual
register bit (on the functional clock domain) is not 0. Writing a 1 to any ITR bit
has no effect.
This register is a status register that gives the state of every incoming interrupt
regardless of which interrupt is currently being processed. Coherency
between this register and the SIR_IRQ/SIR_FIQ registers is not ensured.
DW-3 DW-4 DW-5
RW RW
1 1 1
This register masks each incoming interrupt by setting the corresponding bit
to 1.
MIR operates after ITR. This means that occurrences of incoming interrupts
are always stored in ITR.
Masking a particular interrupt does not deassert either IRQ or FIQ if it is active
owing to this interrupt (providing that no other interrupts are active at the same
time), regardless of whether the interrupt is level- or edge-sensitive. It only
prevents subsequent incoming interrupts from being taken into account.
The write into this register must be done while there are no pending interrupts.
CODE_NB_IT−1 ... 0
Active IRQ number (hexadecimal)
....
RW RWs
1 1s
†
R
0
2 1 0
MIR MIR MIR
2 1 0
RW RW RW
1 1 1
SPRU757B