Texas Instruments OMAP5912 Reference Manual page 973

Layer 4 Interconnect
2.1 TIPB Router Connections
Table 2. Private Peripherals
Table 3. MPU Peripherals Connected to MPU Shared TIPB Bridge
22 Peripheral Interconnects
OMAP 5912 Peripheral
DSP level 2 interrupt handler
ULPD (clock and reset)
OMAP5912 configuration
Secure watchdog
32-kHz watchdog
MPU level 2 interrupt handler
SHA_1 accelerator
RNG random generator
DES/3DES
System DMA handler
OMAP 5912 Peripheral
HDQ/1-Wire
µWIRE
MMCSD/IO1
MPUIO
2 x LPG
SoSSI
RTC
Memory Stick
PWL
PWT
FAC
OS timer
USBOTG
Interface TIPB Router
Wrapper OCP Private DSP
TIPB Private MPU
TIPB Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Wrapper OCP Private MPU
Interface TIPB Router
TIPB Shared MPU
TIPB Shared MPU
Wrapper OCP Shared MPU
TIPB Shared MPU
TIPB Shared MPU
Wrapper VIA Shared MPU
TIPB Shared MPU
TIPB Shared MPU
TIPB Shared MPU
TIPB Shared MPU
TIPB Shared MPU
TIPB Shared MPU
Wrapper OCP Shared MPU
SPRU758A