Texas Instruments OMAP5912 Reference Manual page 336

7.3.3 Fault Handling
7.3.4 Initializing Locked TLB Entries
SPRU750A
The following types of faults may occur:
-
TLB miss with table walker disabled
TLB entries can be locked from [Base_value−1] down to 0.
No translation is found for the logical address required. If the hardware
table walker is disabled, a fault is generated.
-
Translation fault
No translation is found for the logical address required (TLB miss). The
hardware table walker is enabled but no page table entry exists for the re-
quested address.
-
Access permission fault
Read or write access and access permission (AP) set to no access, or
write access and AP set to read only.
When a fault occurs, an interrupt is generated to the MPU. The interrupt
service routine (ISR) is then responsible for fault recovery. For example, for a
TLB miss, the ISR routine might load the missing entry from the page table.
The DSP is stalled by the MMU while the fault is handled.
The ISR can determine the cause of the abort interrupt by reading the
F_ST_REG register. The logical address that caused the fault can be
determined by reading the FAULT_AD_H_REG and FAULT_AD_L_REG
registers.
Following the fault and completion of the fault handling code, the ISR releases
the MMU by writing to the interrupt acknowledge register (IT_ACK_REG). The
MMU then continues servicing the DSP request. The ISR may also terminate
DSP operation by resetting the DSP and the MMU.
Follow this procedure to load a translation lookaside buffer manually.
1) Load the logical address, the preserved bit, and the section/page format
(SLST field) in the CAM_H_REG and CAM_L_REG registers.
2) Load the physical address and the access permission bits in the
RAM_H_REG and RAM_L_REG registers.
3) Update the current_victim field (in the LOCK_REG register), which
specifies the location of the entry to be loaded.
4) Set the ld_tlb_item bit of the LD_TLB_REG register to load these values.
DSP Memory Management Unit
DSP Subsystem 73