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System DMA
Table 56. DMA Channel Status Register (DMA_CSR)
Base Address = 0xFFFE D800, Offset Address = 0x06 + n*0x40
Bit
Name
15:7
RESERVED
6
SYNC
5
BLOCK
4
LAST
3
FRAME
2
HALF
1
DROP
0
TOUT
100
Direct Memory Access (DMA) Support
Function
Reserved
Synchronization status
End block (end of block)
Last frame (start of last frame)
Frame (end of frame)
Half frame (half of frame)
Event drop (request collision)
Time-out in the channel (time-out error)
A status bit is not set if the corresponding interrupt enable bit in the DMA_CICR
register = 0.
TOUT: Time-out in the channel (time-out error)
-
tout = 1: Time-out occurred in channel.
tout = 0: No time-out error occurred in channel.
DROP: Event drop (request collision)
-
drop = 1: Synchronization event drop occurred during the transfer.
drop = 0: No event drop occurred during the transfer.
HALF: Half frame (half of frame)
-
half = 1: First half of the current frame has been transferred.
half = 0: First half of the current frame has not finished transferring yet.
FRAME (end of frame)
-
frame = 1: A complete frame has been transferred.
frame = 0: Transfer of the current frame is still in progress.
LAST: Last frame (start of last frame)
-
last = 1: The transfer of the last frame has started.
last = 0: Last frame has not started yet.
BLOCK: End block (end of block)
-
block = 1: The current transfer in the channel has been finished, but anoth-
er one may have started if DMA_CCR2[AUTO_INIT] = 1.
block = 0: Current transfer has not finished yet.
R/W
Reset
R
N/A
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SPRU755B
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