Texas Instruments OMAP5912 Reference Manual page 428

Table 3. Global Resets (Continued)
Reset Source
Production
eFuse
Warm 32-kHz WD
reset reset
(continued)
SPRU752B
Event Reset Description
eFuse Warm reset permanently asserted by
programmed ULPD
value to BAD
32-kHz WD Reset LCD controller
time-out System DMA
default MPU port interface
configuration configuration L3 OCP initiator L3 OCP initiator
leads to 32s L4 controller
time-out with Traffic controller
32-kHz input
SDRAM refresh mode switched to
frequency. q y
self-refresh if previously set to self-refresh if previously set to
autorefresh state, DSP MMU, MPU
TIPB bridge and peripherals, shared
peripherals Class 2 and class 3
modules. modules
Reset Architecture
Status Bit
EXT_RST (bit 4) MPU
clock reset status
register (ARM_SYSST)
GLOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
EXT_RST (bit 4) MPU
clock reset status
register (ARM_SYSST)
Reset Done (bit 0) in
32K watchdog system
status register
(WD_SYSSTATUS)
GOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
EXTERNAL_RESET_
SOURCE_3 (bit 3) of
ULPD status register
Initialization 11