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Figure 1.
NAND Flash Controller Overview
Interface
To host
module
NAND flash controller
SPRU756A
OCP timing
Controller timing
FIFO
Select and
ECC result
enable
The external NAND flash (NFMC) is an 8-bit interface (byte addressable).
From the host processor, the NFC can access data in 8, 16, or 32 bits.
The NFC supports prefetch and postwrite modes implemented around a FIFO
buffer for latency optimization.
The NFC supports DMA transfers on a page-in-read and program operations,
and has the following general features:
-
Flexible architecture to support different sizes of NFMCs
-
8-bit interface to NAND flash
-
8-bit, 16-bit, or 32-bit interface from the host processor
-
Error code correction (ECC) for maximum data integrity
-
DMA support on one NAND flash memory page for read and program
operations
-
Ablity to support from one to four NFMCs
Accessing an NFMC requires an 8-bit bus, which is multiplexed among data,
address, and commands. Table 1 lists the command operations.
Memory Interfaces for the EMIFS
Memory timing
Sequencer
module
Address
and
commands
N.F.M.C
Write
interface
data
module
Read
data
ECC
module
Memory Interfaces
Memory
bus
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