Texas Instruments OMAP5912 Reference Manual page 880

Software NAND Flash Controller
Step 2: Configure EMIFS and NAND Flash for a Write
Step 3: Write Data to NAND Flash Device
74 Memory Interfaces
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The DMA interrupts the processor when the transfer is complete.
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The processor reads the ECC calculation from the NAND flash controller
peripheral.
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The calculated ECC results are written in SDRAM.
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The associated EMIFS CS chip-select control register is programmed.
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The configuration register multiplexes the chip-select with a GPIO. The
GPIO module drives the GPIO active low when access to the NAND flash
device is needed.
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The configuration register programs the FLASH.RDY signal to be a GPIO
input for the generation of interrupts on the rising edge of the NAND flash
device R/B signal.
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The processor programs and enables an interrupt on the rising edge of the
GPIO multiplexed on the R/B signal to signify when the NAND flash has
completed programming.
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The processor initiates a write command (80h= serial data input) and an
address write to the NAND flash device.
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The NAND flash device is now ready to receive a block of data.
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The MPU programs the system DMA:
J
Transfer the data in 8-, 16-, or 32-bit word format from SDRAM to the
NAND flash peripheral.
J
Transfer mode (single mode= > channel stop when current transfer
finishes)
J
The DMA creates an interrupt on completion of the transfer.
J
Transfer start (software request)
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Data are written into the NAND flash device.
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When all of the data for a block are written into the device, the processor
initiates an auto program command (10h = auto program).
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The R/B signal goes low to signify that the NAND flash is busy with the
internal programming operation (t
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The R/B signal goes high, creating an interrupt to the processor that
signifies that the block write has been completed.
).
PROG
SPRU756A