Texas Instruments OMAP5912 Reference Manual page 546

Ultralow-Power Device
Table 3. Initiators of Deep Sleep −> Awake Transition
28 Power Management
Transition from Deep Sleep to Awake
Wake-up Event
PWRON_RESET
RTC_ON_NOFF
MPU_RST
32-kHz watchdog reset
Wake-up request
PERIPH_REQ
PERIPH_REQ
The transition follows one of two sequences:
-
Sequence 1
1) The following wake-up event occurs:
a) OMAP3.2 asserts a wake-up request. The wake-up request is
initiated by a peripheral unmasked interrupt.
b) UART2 requests system clock.
c) Power-up reset, system reset (low on MPU_RST), secure watchdog
reset, or 32-kHz watchdog reset
2) LOW_PWR is asserted high.
3) Depending on the system input clock source mode:
a) External mode:
SETUP_ANALOG_CELL3, is loaded with the related setup value
from the ULPD register that corresponds to the ramp-up time of the
external voltage supply.
When the counter underflow is generated, it globally enables the sys-
tem input clock to peripherals.
At this point, it is possible that the external system input clock is not
present yet.
The peripheral clocks are effectively restarted whenever the system
input clock arrives, if the corresponding clock request is active.
This setup stage is intended to allow the supply voltage to be stable
before enabling the input clocks to peripherals.
At power up, the supply voltage and the input system clock must be
stable when the PWRON_RESET signal is released. In this case, this
setup stage is skipped.
Power-on reset pin
Power-on reset pin
System reset pin
32-kHz watchdog time-out
Peripheral unmasked interrupts
System clock request from UART2
In this case, the setup down counter,
SPRU753A