Texas Instruments OMAP5912 Reference Manual page 715

Table 49. Global DMA Capability Register 4 (DMA_CAPS_4) (Continued)
Bit Name
1 EDIC
0 TOIC
Table 50. Physical Channel-x Status Registers (DMA_PCh2_SR,..., DMA_PHhD_SR_0)
Base Address = 0xFFFE DC00, Offset = 0x60, 0x80. 0x82, 0xC0
Bit Name
15:8 RESERVED
7:0 ALCN
3.3.2 Logical Channel Registers
SPRU755B
Base Address = 0xFFFE DC00, Offset = 0x5A
Function
Event drop interrupt capability (request collision):
0: Does not support event drop interrupt generation capability.
1: Supports event drop interrupt generation capability.
Time-out interrupt capability (time-out error):
0: Does not support time-out interrupt generation capability.
1: Supports time-out interrupt generation capability.
Function
Reserved
Active logical channel number for associated
physical channel.
Table 33 specifies which physical channels match each offset. These return
the logical channel ID, which is active in the associated physical channel.
These four registers can be used to monitor the progress of a DMA physical
channel transfer.
Each register is a snapshot of the current logical channel number, which is
active on the physical channel:
FF: DMA Physical_Channel_x is IDLE.
Others: DMA Logical_Channel_Number is active on the physical channel.
If PchD is active, DMA_PChD_SR_0 will read as 0x1F if DMA is in
OMAP3.2 compatible mode and 0xC in OMAP3.0/3.1 compatible mode.
This set of registers is instantiated within each logical channel to the DMA. The
registers for the display channel, LCh-D are specific for that channel. Hence,
these registers are collected in a dedicated section for the LCh-D, see
Section 3.3.3, LCD Channel Dedicated Registers.
All registers for a specific LCh must be configured before the LCh is enabled;
if not, it will cause undefined effects. There are some exceptions to this rule
when in OMAP3.0/3.1 compatible mode.
Direct Memory Access (DMA) Support
System DMA
R/W Reset
R 1
R 1
R/W Reset
R ND
R 0xFF
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