Texas Instruments OMAP5912 Reference Manual page 719

Table 54. DMA Channel Control Register (DMA_CCR)
Base Address = 0xFFFE D800, Offset Address = 0x02 + n*0x40
Bit Name
15:14 DST_AMODE
13:12 SRC_AMODE
11 END_PROG
10 OMAP_3_1_COMPATIB
LE_DISABLE
9 REPEAT
8 AUTO_INIT
7 ENABLE
6 PRIO
5 FS
4:0 SYNC
SPRU755B
Function
Destination addressing mode
Source addressing mode
End of programming status bit
OMAP 3.0/3.1 channel compatibility control
Repetitive operation
Autoinitialization at the end of the transfer
Logical channel enable
Channel priority
Frame synchronization
Synchronization control
SYNC: Synchronization control
-
This field is used to specify the external DMA request, which can trigger
the transfer for the LCh. There are 31 possible choices for the system
DMA. Each LCh can be triggered by one of the DMA request inputs. A
hardware DMA request cannot be shared between several concurrent
channels (enabled and active). However, a hardware DMA request can be
shared between different channels if they are part of a chain. Therefore,
the user must carefully generate DMA requests if a sharing strategy is cho-
sen. Otherwise, event drop of channel transfer may occur when the next
DMA request is issued to trigger another channel transfer while the current
channel transfer is still going on. For nonsynchronized LCh transfers, this
field must be set to binary 00000.
FS: Frame synchronization
-
This bit and the bs bit in the DMA_CCR2 register are used to program the
way that a DMA_request is serviced in a synchronized transfer.
fs = 1 and bs = 0: An entire frame is transferred each time a DMA_request
is made. This frame can be interleaved on the DMA ports with other chan-
nel requests.
Direct Memory Access (DMA) Support
System DMA
R/W Reset
R/W 00
R/W 00
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 00000
95