Texas Instruments OMAP5912 Reference Manual page 1051

Dual-Mode Timer
Table 39. Timer Control Register (TCLR) (Continued)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x24
Bit Name
1 AR
0 ST
Table 40. Timer Counter Register (TCRR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x28
Bit Name
31:0 TIME_COUNTER
48 Timers
(LSB), 0x26 (MSB)
Function
1: Autoreload timer
0: One-shot timer
1: Start timer
0: Stop timer: Only the counter is frozen
In case of one-shot mode selected (AR = 0), this bit
is automatically reset by internal logic when the
counter overflows.
(LSB), 0x2A (MSB)
Function
Value of timer counter
The TCRR register is a 32-bit register (16-bit addressable). Therefore, the
MPU can perform one 32-bit access or two 16-bit accesses to the register
while the DSP performs two consecutive 16-bit transactions. Because the
timer interface clock is completely asynchronous with the timer clock, some
synchronization is done to ensure that the TCRR value is not read while it is
being incremented.
In 16-bit mode, the following sequence must be followed to read the TCRR
register properly:
1) Read the lower 16-bits of the TCRR register (offset = 0x28). When the
TCRR is read, the lower 16-bit LSB are read, and the upper 16-bits of the
TCRR MSB register are stored in a temporary register.
2) Read the upper 16 bits of the TCRR register (offset = 0x2A). During this
read, the value of the upper 16-bit MSB that has been stored in the
temporary register is read.
Therefore, to read the value of TCRR correctly, the first OCP read access must
be to the lower 16-bits (that is, offset = 0x28), followed by OCP read access
to the upper 16-bits (that is, offset= 0x2A).
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0x000 0000
SPRU759B