Texas Instruments OMAP5912 Reference Manual page 203

Table 64. MPU Idle Enable Control Register 1 (ARM_IDLECT1) (Continued)
Bit Name
10 WKUP_MODE
9 IDLTIM_ARM
8 IDLAPI_ARM
7 IDLDPLL_ARM
For reserved bits, reading gives undefined values. Writing to has no effect.
Note:
SPRU749A
Base Address = 0xFFFE CE00, Offset = 0x04
Function
Controls how the MPU can exit the CHIP_IDLE state
0: After the interrupt has been asserted, the MPU idle mode
is exited upon a low level at the external CHIP_nWKUP pin.
Also, any of the wake-up conditions only wake up the
OMAP out of CHIP_IDLE if CHIP_nWKUP is low.
1: Idle mode is exited upon an MPU interrupt (regardless
the CHIP_nWKUP pin). Also, any wake-up condition wakes
up the OMAP out of CHIP_IDLE regardless of the value on
the CHIP_nWKUP pin.
Selects the idle entry mode for internal MPU timer clock.
0: The clock supplied to the timers remains active when the
MPU enters the idle mode.
1: The timer clock is stopped in conjunction with the MPU
clock when the idle mode is entered.
Selects the idle entry mode for MPUI clock.
0: The clock supplied to the MPUI is fully controlled by
EN_APICK bit
1: The clock supplied to MPUI is on whenever it is required
for any functionality; else it goes to IDLE
This bit must be set to 1 active to go to chip idle mode. The
EN_APICK bit must not be deactivated to go to chip idle as
that may cause wake-up problems for certain sources.
Enables the DPLL macro to enter idle mode when DSP is
set to global_idle mode, MPU is in idle mode, no active
DMA transaction or TCLB_EN pin is asserted low, no TIPB
posted write is queued, and the peripheral clocks are
stopped.
0: DPLL remains active when the above conditions occur.
1: DPLL enters idle mode when above conditions are met.
Clock Generation and Reset Management
OMAP3.2 Subsystem
R/W Reset
R/W 1
R/W 0
R/W 0
R/W 0
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