Texas Instruments OMAP5912 Reference Manual page 185

Table 61. OMAP 3.2 Hardware Engine Clocking Modes (Continued)
Clock Clocking Operating Mode
Select
100 Reserved
101 Bypass mode
110 Mix mode #3: MPU
synchronous to TC, DSP
synchronous scalable to TC
and MPU
111 Mix mode #4: DSP
synchronous to TC, MPU
synchronous scalable to TC
and DSP
Fully Synchronous Mode
Synchronous Scalable Mode
SPRU749A
MPU Clock
Source
CK_REF
DPLL1/N
DPLL1/M
In fully synchronous mode, the MPU, DSP, and TC domains run at the same
clock frequency derived from DPLL1. This is the power-up default mode. The
fully synchronous mode is a special case of synchronous scalable mode,
where the clock divider bits for all domains are equal. However, there is
separate clock select encoding for fully synchronous mode. It is the
programmer's responsibility to ensure that all the clock divider select bits are
set to the same value.
When the fully synchronous mode is selected, you must program the
divide-down bits of the ARM_CKCTL register so that ARMDIV, DSPMMUDIV,
DSPDIV, and TCDIV are equal.
In synchronous scalable mode, the MPU, DSP, and TC domains are
synchronous and run at different clock speeds. The clock feeding mechanism
is similar to that of the fully synchronous mode, except that the clocks are
multiples of one another.
In synchronous scalable mode, the divide-down bits ARMDIV, DSPDIV, and
TCDIV of the ARM_CKCTL register define the prescaler value from the
frequency of DPLL.
When the synchronous scalable mode is selected, you must program the
divide-down bits of the ARM_CKCTL register so that DSPMMUDIV = DSPDIV
or DSPDIV*2.
Clock Generation and Reset Management
DSP Clock TC Clock
Source Source
CK_REF CK_REF
DPLL1/M DPLL1/N
DPLL1/N DPLL1/N
OMAP3.2 Subsystem
Remarks
Input reference
clock
See Mix Modes
See Mix Modes
127