Texas Instruments OMAP5912 Reference Manual page 155

Table 16. EMIFS Registers (Continued)
Name
EMIFS_CCS0
EMIFS_CCS1
EMIFS_CCS2
EMIFS_CCS3
EMIFS_PTOR1
EMIFS_PTOR2
EMIFS_PTOR3
EMIFS_DWS
EMIFS_AADDR
EMIFS_ATYPER
EMIFS_ATOR
EMIFS_ACS0
EMIFS_ACS1
EMIFS_ACS2
EMIFS_ACS3
Note: The EMIFS chip-select configuration register reset values depend on the input boot pin state at IC reset release time.
For more details, see Section 3.2.18, EMIFS Boot Mode.
Table 17. EMIFS Priority Register (EMIFS_PRIOR)
Bits Field
31:16 RESERVED
15:12 OCPI
11:8 DMA
7 RESERVED
SPRU749A
Base Address = FFFE CC00
Description
EMIFS chip-select configuration CS0
EMIFS chip-select configuration CS1
EMIFS chip-select configuration CS2
EMIFS chip-select configuration CS3
EMIFS dynamic priority time-out 1
EMIFS dynamic priority time-out 2
EMIFS dynamic priority time-out 3
EMIFS dynamic wait states
EMIFS abort address
EMIFS abort type
EMIFS abort time-out
Advanced EMIFS chip-select configuration nCS0
Advanced EMIFS chip-select configuration nCS1
Advanced EMIFS chip-select configuration nCS2
Advanced EMIFS chip-select configuration nCS3
Base Address = 0xFFFE CC00, Offset = 0x04
Description
Reserved. To ensure software compatibility, reserved
bit should be written to 0 and read value should be
considered undefined.
OCPI consecutive access
DMA consecutive access
Reserved
Traffic Controller
R/W Offset
R/W 0x10
R/W 0x14
R/W 0x18
R/W 0x1C
R/W 0x28
R/W 0x2C
R/W 0x30
R/W 0x40
R 0x44
R 0x48
R/W 0x4C
R/W 0x50
R/W 0x54
R/W 0x58
R/W 0x5C
R/W
R/W 0x0000
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
0x0
0x0
0
97