Texas Instruments OMAP5912 Reference Manual page 881

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Read Data Sequence Example

NAND Flash Read Sequence

Step 1: Configure EMIFS, ECC, and NAND Flash for a Read

The processor initiates a status read command (70h= status read).

The processor reads the NAND flash status register (status read

command is sent) and takes the necessary action based on the

programming status (if there is an error, block management is required).

One block write is completed; further block writes can continue from step

The high-level sequence of operations that are needed to read data from the

NAND flash device is shown in Figure 21. The assumption is that the

destination data read from the NAND flash device is saved in external SDRAM

memory, but this is not a requirement. Data can be saved in any memory space

available in the system. The MPU is the processor controlling the read

The associated EMIFS chip-select control register is programmed.

The configuration register multiplexes the associated CS chip-select with

a GPIO. The GPIO module drives the GPIO active low when an access

is needed to the NAND flash device.

The configuration register programs the FLASH.RDY signal to be a GPIO

input for the generation of interrupts on the rising edge of the NAND flash

device R/B signal.

Software NAND Flash Controller

MPU subsystem

Memory Interfaces

Chapters

Table of Contents