Texas Instruments OMAP5912 Reference Manual page 1053

Dual-Mode Timer
Table 44. Timer Match Register (TMAR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x38
Bit Name
31:0 COMPARE VALUE
Table 45. Timer Capture Register (TCAR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x3C
Bit Name
31:0 CAPTURED VALUE
Table 46. Timer Synchronization Interface Control Register (TSICR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x40
Bit Name
31:2 RESERVED
2 POSTED
1 SFT
0 RESERVED
50 Timers
(LSB), 0x3A (MSB)
Function
Value to be compared to the timer counter
The compare logic consists of a 32-bit wide, read/write data TMAR register
and logic to compare the counter current value with the value stored in the
TMAR register.
(LSB), 0x3E (MSB)
Function
Timer counter value captured on an external event
trigger
When the appropriate transition (rising, falling, or both) is detected in the edge
detection logic, the current counter value is stored to the TCAR register.
(LSB), 0x42 (MSB)
Function
Reserved
1: Posted mode active (clocks ratio needs to fit the
MPU peripheral clock > 4 timer clock frequency
requirement)
0: Posted mode inactive
This bit resets the all of the functional parts of the
module.
During reads, it always returns 0.
1: Software reset is enabled.
0: Software reset is disabled.
Reserved
R/W Reset
R/W 0x000 0000
R/W Reset
R 0x0000
0000
R/W Reset
R 0x0000
0000
R/W 1
R/W 0
R 0
SPRU759B