Texas Instruments OMAP5912 Reference Manual page 242

MPU and MPUI Port
Table 97. DSP Status Register (DSP_STATUS) (Continued)
Bit Name
9 PENRESETDPLL
8 PEIDLE7
7 PEIDLE6
6 PEIDLEDPLL
5 PEIDLEPERIPH
4 CPUIACK
3 CPUAVIS
2 CPUXF
1 RESET_MCU
0 RESET
Table 98. DSP Boot Configuration Register (DSP_BOOT_CONFIG)
Bit Name
31:16 Reserved
15:10 BOOT_RHEA_PTR2
184 OMAP3.2 Subsystem
Base Address = 0xFFFE C900, Offset = 0x14
Function
Reflects level of asynchronous reset in the DSP
(controlled by emulation)
Idle peripherals flag. Reflects bit 7 of (ISTR) from the
DSP.
Idle peripherals flag. Reflects bit 6 of (ISTR) from the
DSP.
Idle DPLL flag. Reflects bit 4 of (ISTR) from the DSP.
Idle peripherals flag. Reflects bit 3 of (ISTR) from the
DSP.
Reflects level of Interrupt acknowledged signal from
the DSP.
Reflects bit 4 from (DSP_STATUS).
Reflects level of XF output from (DSP_STATUS).
Reflects level of the secondary DSP subsystem reset
originating from the MPU (active low). Signal used to
reset the DSP TIPB interrupt priority encoder, the
EMIF configuration registers, and the MPUI port
control logic.
Reflects level of DSP subsystem master reset (active
low). Signal used to reset the entire DSP subsystem
except for the DSP TIPB interrupt priority encoder, the
EMIF configuration registers, and the MPUI port
control logic.
Base Address = 0xFFFE C900, Offset = 0x18
Function
User-defined pointer that can be used for
application-specific boot code location
R/W Reset
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R/W Reset
R/W 0x0000
R/W 000000
SPRU749A