Texas Instruments OMAP5912 Reference Manual page 518

Multimedia processor device overview and architecture
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B
Boot mode control, OMAP5912 configuration 94
C
Clock and reset architecture 7
Input/output 24
OMAP3.2 resets 13
OMAP5912 resets 8
OMAP5912 peripherals resets 15
peripherals reset table 17
Configuration register capabilities, OMAP5912
configuration 27
D
Duplicated interfaces, OMAP5912 initialization 92
E
EMIFS multiplexing control generation, OMAP5912
configuration 94
External interfaces, OMAP5912 initialization 91
I
Interfaces configuration in internal boot ROM,
OMAP5912 reset/boot 95
N
notational conventions 3
O
OMAP3.2 resets, clock and reset architecture 13
SPRU752B
OMAP5912 configuration 26
boot mode control 94
EMIFS multiplexing control generation 94
OMAP5912/5910 SW/HW compatibility 33
parallel observability in functional mode 30, 31
pin multiplexing and pullups/pulldowns 28
register capabilities 27
registers 35
OMAP5912 initialization 91
duplicated interfaces 92
external interfaces 91
reset/boot overview 94
OMAP5912 input/output, clock and reset
architecture 24
OMAP5912 peripherals resets, clock and reset
architecture 15
OMAP5912 reset/boot overview 94
interfaces configuration in internal boot ROM 95
OMAP5912 resets, clock and reset architecture 8
OMAP5912/5910 SW/HW compatibility, OMAP5912
configuration 33
P
Parallel observability in functional mode,
OMAP5912 configuration 30, 31
Peripherals reset table, clock and reset
architecture 17
Pin multiplexing and pullups/pulldowns, OMAP5912
configuration 28
R
Registers, OMAP5912 configuration 35
related documentation from Texas Instruments 3
T
trademarks 3
Index
Index
OMAP5912
101

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