Table 8.
Mode Selection
4.1
Timing Diagrams
Figure 8.
VDD_CORE Ramps First
VDD_IO
VDD_CORE
PWRDN
SLEEP
RESPWRON
STEADY
SPRU751A
PWRDN
L
H
L
LDO is OFF
Low-Dropout Voltage Regulator
SLEEP
L
Don't care
H
Mode
Application, active
Powerdown
Sleep
LDO is ON
Clocks
31