Texas Instruments OMAP5912 Reference Manual page 940

Level 1 MPU Interrupt Handler
Table 27. Interrupt Control Register (CONTROL_REG)
Bit Name
31:2 Reserved
1 NEW_FIQ_AGR
0 NEW_IRQ_AGR
Table 28. Interrupt Level Register for Interrupt Number x (0 to 31) (ILRx)
Bit Name
31:7 Reserved
6:2 PRIORITY
1 SENS_LEVEL
0 FIQ
Table 29. Software Interrupt Set Register (SIR)
Bit Name
31:0 SIR
42 Interrupts
Offset: 0x18
Function
New FIQ agreement. Writing a 1 resets the FIQ
output, clears the SIR_FIQ, and enables a new
FIQ generation. The corresponding bit of the
ITR must be cleared first. Writing 0 has no
effect.
New IRQ agreement. Writing a 1 resets the IRQ
output, clears the SIR_IRQ, and enables a new
IRQ generation. The corresponding bit of the
ITR must be cleared first. Writing 0 has no
effect.
Offset: 0x1C + 0x4 * Interrupt number
Function
Defines the priority level when the corresponding
interrupt is routed to IRQ or FIQ.
0 is the highest priority level.
31 is the lowest priority level.
0: The corresponding interrupt is falling-edge sensitive.
1: The corresponding interrupt is low-level sensitive.
0: The corresponding interrupt is routed to IRQ.
1: The corresponding interrupt is routed to FIQ.
Offset: 0x9C
Function
See below.
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 00000
R/W 0
R/W 0
R/W Reset
R/W 0x0000 0000
SPRU757B