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Level 1 MPU Interrupt Handler
3.1.7
Registers
Table 22. Interrupt Registers
Name
ITR
MIR
SIR_IRQ
SIR_FIQ
CONTROL_REG
ILRx
SIR
GMR
40
Interrupts
6) The ISR code must be capable of doing one of the following things:
Letting the peripheral know that the interrupt generated by it has been
J
serviced so the peripheral can deassert the interrupt request
Writing to interrupt handler mask interrupt register (MIR) to mask the
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level-sensitive interrupt
Here the peripheral has to deassert the interrupt before the mask to
the interrupt can be removed, so that the next interrupt can be recog-
nized.
If the peripheral deasserts the interrupt before the code in ISR tells it
to, then the behavior is unpredictable and the interrupt may be lost.
7) The MPU must write a 1 to CONTROL_REG.NEW_IRQ_AGR when it is
about to exit the ISR routine to deassert the IRQ going to MPU and to
enable a new IRQ generation.
8) The MPU exits the ISR and continues its normal code execution.
9) When CONTROL_REG.NEW_IRQ_AGR is written into by MPU, the
process jumps to Step 2.
Table 22 lists the registers available to handle interrupts. Table 23 through
Table 30 provide register bit descriptions. All these registers are 32 bits wide
and are controlled directly by the private TIBP bus. To determine the base
address of these registers, see the Applications Processor Data Manual
(SPRS231).
Description
Interrupt register
Interrupt mask register
Interrupt encoded source register for IRQ
Interrupt encoded source register for FIQ
Interrupt control register
Interrupt level register
Software interrupt set register
Global mask interrupt register
R/W
Offset
R/W
0x00
R/W
0x04
R
0x10
R
0x14
R/W
0x18
R/W
0x1C + 0x4 *
x
R/W
0x9C
R/W
0xA0
SPRU757B
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