Texas Instruments OMAP5912 Reference Manual page 174

Traffic Controller
Table 45. EMIFF Dynamic Arbitration Priority Time-Out Register 2
(EMIFF_PTOR2)
Bit Field Description
31:7 Reserved Must be all 0.
23:16 DSP Number of clock cycles before DSP requests are made high priority
in the dynamic priority scheme for the EMIFF SDRAM interface.
15:8 Reserved Reserved
7:0 LCD Number of clock cycles before LCD requests are made high priority
in the dynamic priority scheme for the EMIFF SDRAM interface.
Table 46. EMIFF Dynamic Arbitration Priority Time-Out Register 3
(EMIFF_PTOR3)
Bit Field
31:7 Reserved
7:0 L3
116 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x90
Base Address = 0xFFFE CC00, Offset = 0x94
Description
Must be all 0.
Number of clock cycles before L3 OCP initiator
requests are made high priority in the dynamic
priority scheme for the EMIFF SDRAM interface.
Time-out registers 1 −3 are used to store the number of clock cycles before
DSP, DMA, or Level 3 OCP initiator requests are made high priority in the
dynamic priority scheme for the EMIFF SDRAM interface.5rrP@2a0mill
R/W Reset
R 0x000000
R/W 0x00
R 0x00
R/W 0x00
R/W Reset
R 0x000000
R/W 0x00
SPRU749A