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6.5
Peripheral Alignment and Data Width
6.6
OS Timer Registers
Table 51. Operating System Registers
Name
TICK_VALUE_REG
TICK_COUNTER_REG
TIMER_CTRL_REG
Table 52. Timer Registers Access Timing Constraints
Register Name
TIMER_CTRL_REG
TICK_COUNTER_REG
TICK_VALUE_REG
SPRU759B
The TIPB interface data path is 32 bits wide. To keep software compatible with
earlier 16-bit timer versions, the access width is taken into account when
writing to the registers. This means that writing 8 bits (or 16 bit) sets 24 MSB
(or 16 MSB) to 0.
For read accesses, all 32 bits are always output.
All unused register bits remain at 0.
Table 51 lists the OS timer registers. Table 52 through Table 55 describe the
register bits. Synchronization of reads and writes to the 32-kHz clock is
performed in a different way for each register, which leads to slight restrictions
concerning register access (see Table 52).
Base Address = 0xFFFB 9000
Description
Tick value
Tick counter
Timer control
Read
Can be read anytime. The value
read is the last value written.
Reads are resynchronized on a
high-speed clock to the prevent
peripheral bus from timing out. Can
be read anytime, providing
high-speed clock is running. If not,
the value is not assured.
Can be read anytime. The value
read is the last value written.
Operating System Timer
R/W
R/W
R
R/W
Write
Two consecutive writes must be
separated by at least 1 CLK32
period (31.25 µs). If this is not the
case, the value written is not
assured.
Writing to this register has no effect.
Two consecutive writes must be
separated by at least 1 CLK32
period (31.25 µs). If this is not the
case, the value written is not
assured.
Timers
Offset
0x00
0x04
0x08
57
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