Texas Instruments OMAP5912 Reference Manual page 614

OMAP5912 Power Modes
Table 52. Global OMAP5912 System Power Modes
Global OMAP5912
Power Mode
ACTIVE MODE
BIG SLEEP MODE
DEEP SLEEP MODE
OFF MODE
Table 53. MPU Domain States
OMAP3.2
MPU
Input
Domain
Clock
State
Active On
Inactive Off
Pending Off
Sleep Off
96 Power Management
Chip MPU Domain State
State
1.1 Active state
1.2 Active state
1.3 Active state
2.1 Inactive state
2.2 Inactive state
3.1 Pending state
3.2 Pending state
0 Sleep state
The possible MPU system (ARM926EJS, TC, DMA, and memory
interfaces—all OMAP5912 peripherals) states are described in Table 53.
CLOCKS
MPU and
OMAP3.2
TC
PLL Clocks
On or Off On or Off
Off Off
Off Off
Off Off
State retention is ensured when the MPU subsystem is in active, inactive, and
pending states.
In sleep state, there is no state retention.
The possible DSP system (MGS3) states are described in Table 54.
DSP Domain State
Active state
Inactive state
Sleep state
Inactive state
Sleep state
Pending state
Sleep state
Sleep state
32 kHZ ULPD
pheral
Clock PLL Clocks
On On or Off On or Off
On Off
On Off
Off Off
Input Sys- 32-kHz
tem Clock Clock
On
On
On
On
On
On or Off
On or Off
Off On or Off
Peri-
Power
ULPD
Supply
State
Voltage
Awake 1.6 or 1.1 V
Off Big 1.6 or 1.1 V
Sleep
Off Deep 1.1 V
Sleep
Off Off
SPRU753A
On
On
On
On
On
On
On
0 V